1. Field of the Invention
The present invention relates to an input buffer circuit having rail-to-rail operation and a differential amplifier structure.
2. Description of the Related Art
In a semiconductor memory device an input buffer circuit is generally used to change the voltage level of a signal inputted from the outside to a voltage level matching the interior operating voltage of the semiconductor memory device. In general a signal inputted to a semiconductor memory device from the outside has a TTL (Transistor-Transistor Logic) level, and a signal used within a semiconductor memory device has a CMOS (Complementary Metal Oxide Semiconductor) level. The signal inputted to the semiconductor memory device from the outside cannot be used unchanged in the interior of the semiconductor memory device, thus an input buffer is used to convert the voltage level of the signal applied from the outside into a voltage level matching the interior of the semiconductor memory device.
Such an input buffer circuit may have a differential amplifier structure. In an input buffer circuit having a differential amplifier structure, the operating range of the output terminal and input terminal decides the operating voltage range of the amplifier. The operating range of the input terminal is decided by the design of the differential amplifier, and herein, the operating range of the differential amplifier is called a common-mode input range. The common-mode input range decides an input dynamic range in a buffer circuit such as a voltage follower. An input buffer circuit that is operable in the entire input range of the amplifier, from a smallest value (a ground potential), to a largest value (the supply power voltage), is called an input buffer circuit having “rail-to-rail” operation.
The ideal input buffer circuit has rail-to-rail operation and simultaneously has a uniform trans-conductance in over the entire common-mode input range. The trans-conductance (gm) is the ratio of an input current change to input voltage change.
FIG. 1 illustrates a conventional input buffer circuit having a differential amplifier structure of a NMOS current mirror.
Referring to FIG. 1, a conventional input buffer circuit having a differential amplifier structure of a NMOS current mirror includes PMOS transistors MP1 and MP2, NMOS transistors MN1 and MN2, and a current source I0.
The PMOS transistors MP1 and MP2 have the configuration of a current mirror and are the same size. The PMOS transistor MP1 is connected between a power source voltage terminal VCC and a first node N1, and the PMOS transistor MP2 is connected between a power source voltage terminal VCC and a second node N2.
The NMOS transistors MN1 and MN2 are input transistors configured to receive applied differential input signals VINN and VINP, and are the same size. The NMOS transistor MN1 is connected between the first node N1 and the current source I0. The NMOS transistor MN2 is connected between the second node N2 and the current source I0. One end of the current source I0 is connected with the NMOS transistors MN1 and MN2, and another end thereof is connected to a ground terminal.
Operation of the input buffer circuit will be described as follows, under the assumption that a voltage level of first input signal VINN is higher than the second input signal VINP.
The NMOS transistor MN1 is driven by the first input signal VINN, thus current flows in the NMOS transistor MN1. The NMOS transistor MN2 is driven by the second input signal VINP, and so current flows in the NMOS transistor MN2 with smaller volume than the current through the NMOS transistor MN1. The voltage level of the first node N1 decreases due to current flowing in the NMOS transistor MN1, and so more current flows through the PMOS transistor MP1. Also current flows in the PMOS transistor MP2. The current flowing in the NMOS transistor MN2 is uniform, thus a voltage at the second node N2 increases, and is outputted as an output signal VO.
FIG. 2 illustrates a conventional input buffer circuit having a differential amplifier structure of a PMOS current mirror.
As shown in FIG. 2, a conventional input buffer circuit having a differential amplifier structure of a PMOS current mirror includes PMOS transistors MP3 and MP4, NMOS transistors MN3 and MN4, and a current source I0.
The NMOS transistors MN3 and MN4 have the configuration of a current mirror and are the same size. The NMOS transistor MN3 is connected between a third node N3 and a ground node, and the NMOS transistor MN4 is connected between a fourth node N4 and the ground node. The PMOS transistors MP3 and MP4 are input transistors receiving an applied differential input signal VINN-VINP, and are the same size. The PMOS transistor MP3 is connected between the third node N3 and a current source I0 one end of which is coupled with a power source voltage terminal VCC. The PMOS transistor MP4 is connected between the fourth node N4 and a current source I0 one end of which is coupled with power source voltage terminal VCC.
Further description for operation of the input buffer circuit having a differential amplifier structure of a conventional PMOS current mirror is omitted as it is well known to those skilled in the art.
In such conventional input buffer circuits there is a limitation of the input buffer circuit in performing rail-to-rail operation within an input signal range. For example for the input buffer circuit shown in FIG. 1, in the case where an input signal range is below the level of threshold voltage Vth of the NMOS transistors MN1 and MN2, the input buffer circuit does not operate rail-to-rail. Furthermore in such conventional input buffer circuits there is a problem that a common mode voltage (CMV) of an output voltage is not uniform.